This invention relates generally to a method of wiring line or metal interconnect design layout in integrated circuit structures employed in apparatus and more particularly to the employment of a unique interconnect layout rule to reduce spatial interconnect capacitance thereby improving integrated circuit operational speed and performance.
It is the general practice in the fabrication of metal interconnects or electrode lines in integrated circuit structures to provide the finished measurements of lines, L, and spacing, S, to be approximately equal to each other, i.e., L.apprxeq.S. In current practice, this scale relationship in integrated circuit design has been 1 .mu.m or less so that L plus S is equal to 2.0 .mu.m or less. As an example, in FIG. 1, a portion of an integrated circuit structure is shown, such as, in the case of interconnects comprising insulating film 12, such as SiO.sub.2, formed on Si semiconductor substrate 11. Thin film metal interconnects 13 comprising Al, Al alloy or the like are formed on the SiO.sub.2 film 12. The relation among the interconnects 13 is of substantially equal width, L, and spatial separation, S, i.e., L.apprxeq.S. Lastly, an insulating film 14, such as SiO.sub.2 formed by CVD, is deposited on interconnects 13 to function as an interlayer dielectric or passivation film. Integrated circuit structures such as shown in FIG. 1 are generally designed according to applicable minimum and maximum design layout rules wherein the spatial separation of metal interconnects is usually determined by the smallest spacing that can be patterned into the metalization.
In these prior art interconnect structures, there exists the problem of delay in circuit operation speed due to the increase in number of interconnects as well as the density thereof because of reduced integration scale. In particular, as the integration scale has increasingly become smaller, the measurements of interconnect width and spatial separation are each equal to or less than 1 .mu.m. As a result, spatial capacitance of interconnects significantly increases and becomes a dominant factor affecting signal propagation delay and switching speed of integrated circuits. Interconnect capacitance has a major effect on operation speed of logic circuitry since it functions as a load. As a result, there is an increase in signal delay or signal propagation delay time and a reduction in signal switching time due to these interconnects. What is needed is a new approach to forming metal interconnects to reduce this increase in capacitance load caused by large scale integration into the sub-micron range together with increases in interconnect density.
It is an object of the present invention to provide a layout method for thin film metal interconnects in integrated circuit structures without experiencing an increase in circuit operation speed delay, even in cases where the width and spatial separation is reduced respectively below 0.8 .mu.m and 1 .mu.m.